The development of modern data processing devices has created a huge need for digital memory storage capacity. This has created intense pressure on integrated circuit manufacturers to provide memory chips having greater and greater memory capacity. Dynamic random access memories (DRAMs) are by far the densest of memory technologies. Because of the simple structure of dynamic random access memory cells, more memory cells can be packed into a single integrated circuit.
The predominantly used memory cell technology in DRAMs is the single transistor, single capacitor cell type. In this cell, current flow to one plate of a capacitor is controlled by a transistor. The data is stored in the capacitor and is read back as the charge on the capacitor. The single transistor, single capacitor memory cell has served well through many generations of dynamic random access memories. However, current technologies have shown limitations to the usefulness of the single capacitor, single transistor memory cell. One limitation is caused by the physical limits of capacitors. Roughly speaking, the capacitance value of a capacitor is proportional to the area of the capacitor. As DRAM cells are shrunk, the capacitance of the single capacitor DRAM cell necessarily shrinks. The smaller the capacitance of the storage capacitor, the more likely an alpha particle or stray voltage spike will destroy the stored charge or create a noise spike which will generate an error when the data is to be read from the memory cell. Therefore, a more effective method of storage is necessary than the use of a single capacitor.
One DRAM cell which does not rely solely on stored capacitives for all of its operational characteristics is the three transistor cell. In the three transistor cell, data is stored using the capacitance of a gate in a field effect transistor. A write transistor controls the flow of current to the gate of the storage transistor. When a logical 1 is to be written to the memory cell, a high voltage is placed on the drain of the write transistor and a high voltage is placed on the gate of the write transistor (assuming all transistors in the memory cell are N-channel transistors). The voltage level conducted to the gate of the storage transistor charges the gate of the storage transistor. The gate voltage of the write transistor is then brought to near 0 volts thus causing the write transistor to cease conducting. This traps charge on the gate of the storage transistor. The third transistor, the read transistor, connects the drain of the storage transistor to a read output terminal. When a high voltage is placed on the gate of the read transistor, the drain of the storage transistor is conductively connected to the read terminal. The read terminal is usually connected to a bitline where a multiplicity of memory cells are connected to the bitline. A sense amplifier is then used to determine the conductivity of the series connected read access transistor and the storage transistor. If a positive charge is stored on the gate of the storage transistor, both the read transistor and the storage transistor will conduct thus connecting a low impedance to a reference potential. This is detected by the sense amplifier and the stored logical 1 state is provided to the output circuitry. If a negative or close to 0 charge is stored on the gate of the storage transistor, the storage transistor will not conduct and the sense amplifier will see a high impedance from the bitline to the reference potential. The sense amplifier will then provide a logical 0 output signal to the output circuitry.
The three transistor memory cell was largely superseded by the single transistor, single capacitor cell because three transistors occupy more area than the single transistor and a single capacitor. In addition, highly integrated single transistor, single capacitor memory cells were developed. For example, see Kuo, U.S. Pat. No. 4,240,092, issued Dec. 16, 1980 and assigned to the assignee of this application.
The advent of trench technology has created further advances in DRAM cell technology. An example of this is Malhi, et al., U.S. Pat. No. 4,797,373, issued Jan. 10, 1989 and assigned to the assignee of this application. This reference shows a high density single transistor, single capacitor memory cell formed in a trench to minimize the planar area occupied by the memory cell. This further advances the size advantage of the single transistor, single capacitor memory cell.